Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
A FINFET is a type of transistor that lends itself to the goals of reducing transistor size while maintaining transistor performance. The FINFET is a non-planar, three dimensional transistor formed in a thin fin that extends upwardly from a semiconductor substrate. One important challenge with the implementation of FINFETs is the formation of contacts to the non-planar source and drain regions of the fins. There are two approaches for contact formation for FINFETs: formation of contacts to merged fins and formation of contacts to unmerged fins.
For merged fins, a layer of epitaxial silicon is grown on the fins. As a result of the epitaxial growth, adjacent fins become merged. The resulting contact area is large and lacks topographical variation. Therefore, conventional silicide processes can be used to successfully form silicide contacts on the top surfaces of the merged fins.
For unmerged fins, a separate layer of epitaxial doped silicon or silicon germanium is grown on the top of each fin without the epitaxial growth merging adjacent fins. Unmerged fins are required, for example, for Static Random Access Memory (SRAM) devices and the like. Unmerged fins permit the design of SRAM cells with tighter pitch, making the overall chip layout smaller. Interface resistivity (Rs) is a significant factor in the overall contact resistance of an integrated circuit, and the plurality of unmerged fins provides much more contact formation area due to the higher surface area exposed to the silicidation process. The total resistance from the contacts can be significantly lower than that of a merged set of fins, which have a smaller contact surface area and thus higher resistance. However, during contact formation, conductive contact-forming material can be deposited between the lower sections of unmerged fins, leading to higher parasitic capacitance. Lowering the contact resistance of many small unmerged fins and decreasing parasitic capacitance can make a significant difference in circuit performance.
Accordingly, it is desirable to provide integrated circuits that include FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating such integrated circuits. Moreover, it is desirable to provide integrated circuits that include FINFET devices with lower contact resistance unmerged fins while not increasing parasitic capacitance. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.